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2021-07-15
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Intel's 5nm process revealed, aiming to surpass TSMC's 3nm technology.
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05:09","market":"us","language":"zh","title":"Intel's 5nm process revealed, aiming to surpass TSMC's 3nm technology.","url":"https://stock-news.laohu8.com/highlight/detail?id=2151543332","media":"腾讯新闻","summary":"从表中可以看到，英特尔工艺在目前10nm节点上晶体管密度已经达到了已经达到了1.06亿/mm ，略超三星与台积电在7nm上分别0.95亿/mm 和0.97亿/mm 的密度。而在下一代7nm的节点，英特尔目标将晶体管密度提升至1.8亿/mm ，如果计划达成，其密度不仅将超过目前台积电最新的5nm工艺，更大幅甩开三星的5nm。在随后的5nm工艺中，英特尔将目标定在了3亿/mm ，此目标同样高于台积电的3nm计划，与三星3nm的差距还会进一步拉大。","content":"<p><html><body><article>In a recent research report, Digitimes analyzed...<a href=\"https://laohu8.com/S/SMSN.UK\">Samsung</a>、<a href=\"https://laohu8.com/S/TSM\">TSMC</a>, Intel and<a href=\"https://laohu8.com/S/IBM\">IBM</a>The four companies examined the semiconductor process density issues and compared the cases of 10nm, 7nm, 5nm, 3nm, and 2nm.</p><p><img src=\"https://fid-75186.picgzc.qpic.cn/20210715052058764d246homx5ud9zmy\"/>As can be seen from the table,<a href=\"https://laohu8.com/S/INTC\">Intel</a>The current process has achieved a transistor density of 106 million/mm at the 10nm node, slightly exceeding the densities of 95 million/mm and 97 million/mm at 7nm for Samsung and TSMC, respectively.</p><p>At the next-generation 7nm node, Intel aims to increase the transistor density to 180 million/mm. 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If the plan is achieved, its density will not only exceed TSMC's latest 5nm process, but also significantly surpass Samsung's 5nm.</p><p>In the subsequent 5nm process, Intel set a target of 300 million/mm, which is also higher than TSMC's 3nm plan, and the gap with Samsung's 3nm will widen further.</p><p></article></body></html></p>\n<div class=\"bt-text\">\n\n\n<p> source：<a href=\"http://gu.qq.com/resources/shy/news/detail-v2/index.html#/?id=nesSN202107150521007c20884f&s=b\">腾讯新闻</a></p>\n\n\n</div>\n</article>\n</div>\n</body>\n</html>\n","type":0,"thumbnail":"https://static.tigerbbs.com/975836d8c6eb511241583dccb0d387f2","relate_stocks":{"TSM":"台积电","09086":"华夏纳指-U","03145":"华夏亚洲高息股","03086":"华夏纳指","EWT":"台湾ETF-iShares MSCI","INTC":"英特尔"},"source_url":"http://gu.qq.com/resources/shy/news/detail-v2/index.html#/?id=nesSN202107150521007c20884f&s=b","is_english":false,"share_image_url":"https://static.laohu8.com/9a95c1376e76363c1401fee7d3717173","article_id":"2151543332","content_text":"Digitimes在日前发表的研究报告中，分析了三星、台积电、Intel及IBM四家的半导体工艺密度问题，并对比了10nm、7nm、5nm、3nm及2nm的情况。从表中可以看到，英特尔工艺在目前10nm节点上晶体管密度已经达到了已经达到了1.06亿/mm ，略超三星与台积电在7nm上分别0.95亿/mm 和0.97亿/mm 的密度。而在下一代7nm的节点，英特尔目标将晶体管密度提升至1.8亿/mm ，如果计划达成，其密度不仅将超过目前台积电最新的5nm工艺，更大幅甩开三星的5nm。在随后的5nm工艺中，英特尔将目标定在了3亿/mm ，此目标同样高于台积电的3nm计划，与三星3nm的差距还会进一步拉大。","news_type":1,"symbols_score_info":{"TSM":1,"EWT":0.6,"INTC":1,"03086":0.6,"09086":0.6,"TWmain":1,"03145":0.6}},"isVote":1,"tweetType":1,"viewCount":4632,"authorTweetTopStatus":1,"verified":2,"comments":[],"imageCount":0,"langContent":"EN","totalScore":0}],"hots":[{"id":144239233,"gmtCreate":1626297811822,"gmtModify":1703757227805,"author":{"id":"3561267630001290","authorId":"3561267630001290","name":"allenkee","avatar":"https://static.tigerbbs.com/00702045f838537c610f1f878addf22d","crmLevel":11,"crmLevelSwitch":0,"followedFlag":false,"idStr":"3561267630001290","authorIdStr":"3561267630001290"},"themes":[],"title":"","htmlText":"Great","listText":"Great","text":"Great","images":[],"top":1,"highlighted":1,"essential":1,"paper":1,"likeSize":1,"commentSize":0,"repostSize":0,"link":"https://ttm.financial/post/144239233","repostId":"2151543332","repostType":2,"repost":{"id":"2151543332","kind":"news","pubTimestamp":1626296970,"share":"https://ttm.financial/m/news/2151543332?lang=en_US&edition=fundamental","pubTime":"2021-07-15 05:09","market":"us","language":"zh","title":"Intel's 5nm process revealed, aiming to surpass TSMC's 3nm technology.","url":"https://stock-news.laohu8.com/highlight/detail?id=2151543332","media":"腾讯新闻","summary":"从表中可以看到，英特尔工艺在目前10nm节点上晶体管密度已经达到了已经达到了1.06亿/mm ，略超三星与台积电在7nm上分别0.95亿/mm 和0.97亿/mm 的密度。而在下一代7nm的节点，英特尔目标将晶体管密度提升至1.8亿/mm ，如果计划达成，其密度不仅将超过目前台积电最新的5nm工艺，更大幅甩开三星的5nm。在随后的5nm工艺中，英特尔将目标定在了3亿/mm ，此目标同样高于台积电的3nm计划，与三星3nm的差距还会进一步拉大。","content":"<p><html><body><article>In a recent research report, Digitimes analyzed...<a href=\"https://laohu8.com/S/SMSN.UK\">Samsung</a>、<a href=\"https://laohu8.com/S/TSM\">TSMC</a>, Intel and<a href=\"https://laohu8.com/S/IBM\">IBM</a>The four companies examined the semiconductor process density issues and compared the cases of 10nm, 7nm, 5nm, 3nm, and 2nm.</p><p><img src=\"https://fid-75186.picgzc.qpic.cn/20210715052058764d246homx5ud9zmy\"/>As can be seen from the table,<a href=\"https://laohu8.com/S/INTC\">Intel</a>The current process has achieved a transistor density of 106 million/mm at the 10nm node, slightly exceeding the densities of 95 million/mm and 97 million/mm at 7nm for Samsung and TSMC, respectively.</p><p>At the next-generation 7nm node, Intel aims to increase the transistor density to 180 million/mm. If the plan is achieved, its density will not only exceed TSMC's latest 5nm process, but also significantly surpass Samsung's 5nm.</p><p>In the subsequent 5nm process, Intel set a target of 300 million/mm, which is also higher than TSMC's 3nm plan, and the gap with Samsung's 3nm will widen further.</p><p></article></body></html></p>","source":"tencent","collect":0,"html":"<!DOCTYPE html>\n<html>\n<head>\n<meta http-equiv=\"Content-Type\" content=\"text/html; charset=utf-8\" />\n<meta name=\"viewport\" content=\"width=device-width,initial-scale=1.0,minimum-scale=1.0,maximum-scale=1.0,user-scalable=no\"/>\n<meta name=\"format-detection\" content=\"telephone=no,email=no,address=no\" />\n<title>Intel's 5nm process revealed, aiming to surpass TSMC's 3nm technology.</title>\n<style type=\"text/css\">\na,abbr,acronym,address,applet,article,aside,audio,b,big,blockquote,body,canvas,caption,center,cite,code,dd,del,details,dfn,div,dl,dt,\nem,embed,fieldset,figcaption,figure,footer,form,h1,h2,h3,h4,h5,h6,header,hgroup,html,i,iframe,img,ins,kbd,label,legend,li,mark,menu,nav,\nobject,ol,output,p,pre,q,ruby,s,samp,section,small,span,strike,strong,sub,summary,sup,table,tbody,td,tfoot,th,thead,time,tr,tt,u,ul,var,video{ font:inherit;margin:0;padding:0;vertical-align:baseline;border:0 }\nbody{ font-size:16px; line-height:1.5; color:#999; background:transparent; }\n.wrapper{ overflow:hidden;word-break:break-all;padding:10px; }\nh1,h2{ font-weight:normal; line-height:1.35; margin-bottom:.6em; }\nh3,h4,h5,h6{ line-height:1.35; margin-bottom:1em; }\nh1{ font-size:24px; }\nh2{ font-size:20px; }\nh3{ font-size:18px; }\nh4{ font-size:16px; }\nh5{ font-size:14px; }\nh6{ font-size:12px; }\np,ul,ol,blockquote,dl,table{ margin:1.2em 0; }\nul,ol{ margin-left:2em; }\nul{ list-style:disc; }\nol{ list-style:decimal; }\nli,li p{ margin:10px 0;}\nimg{ max-width:100%;display:block;margin:0 auto 1em; }\nblockquote{ color:#B5B2B1; border-left:3px solid #aaa; padding:1em; }\nstrong,b{font-weight:bold;}\nem,i{font-style:italic;}\ntable{ width:100%;border-collapse:collapse;border-spacing:1px;margin:1em 0;font-size:.9em; }\nth,td{ padding:5px;text-align:left;border:1px solid #aaa; }\nth{ font-weight:bold;background:#5d5d5d; }\n.symbol-link{font-weight:bold;}\n/* header{ border-bottom:1px solid #494756; } */\n.title{ margin:0 0 8px;line-height:1.3;color:#ddd; }\n.meta {color:#5e5c6d;font-size:13px;margin:0 0 .5em; }\na{text-decoration:none; color:#2a4b87;}\n.meta .head { display: inline-block; overflow: hidden}\n.head .h-thumb { width: 30px; height: 30px; margin: 0; padding: 0; border-radius: 50%; float: left;}\n.head .h-content { margin: 0; padding: 0 0 0 9px; float: left;}\n.head .h-name {font-size: 13px; color: #eee; margin: 0;}\n.head .h-time {font-size: 12.5px; color: #7E829C; margin: 0;}\n.small {font-size: 12.5px; display: inline-block; transform: scale(0.9); -webkit-transform: scale(0.9); transform-origin: left; -webkit-transform-origin: left;}\n.smaller {font-size: 12.5px; display: inline-block; transform: scale(0.8); -webkit-transform: scale(0.8); transform-origin: left; -webkit-transform-origin: left;}\n.bt-text {font-size: 12px;margin: 1.5em 0 0 0}\n.bt-text p {margin: 0}\n</style>\n</head>\n<body>\n<div class=\"wrapper\">\n<header>\n<h2 class=\"title\">\nIntel's 5nm process revealed, aiming to surpass TSMC's 3nm technology.\n</h2>\n<h4 class=\"meta\">\n<p class=\"head\">\n<strong class=\"h-name small\">腾讯新闻</strong><span class=\"h-time small\">2021-07-15 05:09</span>\n</p>\n</h4>\n</header>\n<article>\n<p><html><body><article>In a recent research report, Digitimes analyzed...<a href=\"https://laohu8.com/S/SMSN.UK\">Samsung</a>、<a href=\"https://laohu8.com/S/TSM\">TSMC</a>, Intel and<a href=\"https://laohu8.com/S/IBM\">IBM</a>The four companies examined the semiconductor process density issues and compared the cases of 10nm, 7nm, 5nm, 3nm, and 2nm.</p><p><img src=\"https://fid-75186.picgzc.qpic.cn/20210715052058764d246homx5ud9zmy\"/>As can be seen from the table,<a href=\"https://laohu8.com/S/INTC\">Intel</a>The current process has achieved a transistor density of 106 million/mm at the 10nm node, slightly exceeding the densities of 95 million/mm and 97 million/mm at 7nm for Samsung and TSMC, respectively.</p><p>At the next-generation 7nm node, Intel aims to increase the transistor density to 180 million/mm. If the plan is achieved, its density will not only exceed TSMC's latest 5nm process, but also significantly surpass Samsung's 5nm.</p><p>In the subsequent 5nm process, Intel set a target of 300 million/mm, which is also higher than TSMC's 3nm plan, and the gap with Samsung's 3nm will widen further.</p><p></article></body></html></p>\n<div class=\"bt-text\">\n\n\n<p> source：<a href=\"http://gu.qq.com/resources/shy/news/detail-v2/index.html#/?id=nesSN202107150521007c20884f&s=b\">腾讯新闻</a></p>\n\n\n</div>\n</article>\n</div>\n</body>\n</html>\n","type":0,"thumbnail":"https://static.tigerbbs.com/975836d8c6eb511241583dccb0d387f2","relate_stocks":{"TSM":"台积电","09086":"华夏纳指-U","03145":"华夏亚洲高息股","03086":"华夏纳指","EWT":"台湾ETF-iShares MSCI","INTC":"英特尔"},"source_url":"http://gu.qq.com/resources/shy/news/detail-v2/index.html#/?id=nesSN202107150521007c20884f&s=b","is_english":false,"share_image_url":"https://static.laohu8.com/9a95c1376e76363c1401fee7d3717173","article_id":"2151543332","content_text":"Digitimes在日前发表的研究报告中，分析了三星、台积电、Intel及IBM四家的半导体工艺密度问题，并对比了10nm、7nm、5nm、3nm及2nm的情况。从表中可以看到，英特尔工艺在目前10nm节点上晶体管密度已经达到了已经达到了1.06亿/mm ，略超三星与台积电在7nm上分别0.95亿/mm 和0.97亿/mm 的密度。而在下一代7nm的节点，英特尔目标将晶体管密度提升至1.8亿/mm ，如果计划达成，其密度不仅将超过目前台积电最新的5nm工艺，更大幅甩开三星的5nm。在随后的5nm工艺中，英特尔将目标定在了3亿/mm ，此目标同样高于台积电的3nm计划，与三星3nm的差距还会进一步拉大。","news_type":1,"symbols_score_info":{"TSM":1,"EWT":0.6,"INTC":1,"03086":0.6,"09086":0.6,"TWmain":1,"03145":0.6}},"isVote":1,"tweetType":1,"viewCount":4632,"authorTweetTopStatus":1,"verified":2,"comments":[],"imageCount":0,"langContent":"EN","totalScore":0}],"lives":[]}
